1 data sheet acquired from harris semiconductor schs174 features ? common clock and asynchronous master reset ? positive edge triggering ? buffered inputs ? typical f max = 60mhz at v cc = 5v, c l = 15pf, t a = 25 o c ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 m a at v ol , v oh description the harris CD74HC273 and cd74hct273 high speed octal d-type flip-flops with a direct clear input are manufactured with silicon-gate cmos technology. they possess the low power consumption of standard cmos integrated circuits. information at the d inputis transferred to the q outputs on the positive-going edge of the clock pulse. all eight ?ip-?ops are controlled by a common clock (cp) and a common reset ( mr). resetting is accomplished by a low voltage level independent of the clock. all eight q outputs are reset to a logic 0. pinout cd54hc273, cd54hct273, CD74HC273, cd74hct273 (pdip, soic, cerdip) top view ordering information part number temp. range ( o c) package pkg. no. cd54hc273f -55 to 125 20 ld cerdip f20.3 cd54hct273f -55 to 125 20 ld cerdip f20.3 CD74HC273e -55 to 125 20 ld pdip e20.3 cd74hct273e -55 to 125 20 ld pdip e20.3 CD74HC273m -55 to 125 20 ld soic m20.3 cd74hct273m -55 to 125 20 ld soic m20.3 notes: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 2. wafer and die for this part number is available which meets all electrical specifications. please contact your local sales office or harris customer service for ordering information. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 mr q0 d0 d1 q1 q2 d3 d2 q3 gnd v cc d7 d6 q6 q7 q5 d5 d4 q4 cp february 1998 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 CD74HC273, cd74hct273 high speed cmos logic octal d-type flip-flop with reset file number 1479.2 [ /title (cd74 hc273 , cd74 hct27 3) / sub- j ect (high speed cmos logic octal d- type flip-
2 functional diagram truth table inputs output reset ( mr) clock cp data d n q lxxl h - hh h - ll hlxq 0 note: h = high voltage level, l = low voltage level, x = dont care, - = transition from low to high level, q 0 = level before the indicated steady-state input conditions were established. q0 q1 q2 q3 q4 q5 q6 q7 reset mr d0 d1 d2 d3 d4 d5 d6 d7 clock cp data inputs data outputs CD74HC273, cd74hct273
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 25ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) q ja ( o c/w) q jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 125 n/a cerdip package . . . . . . . . . . . . . . . . 105 44 soic package . . . . . . . . . . . . . . . . . . . 120 n/a maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 3. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 m a CD74HC273, cd74hct273
4 hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc to gnd 0 5.5 - - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 m a additional quiescent device current per input pin: 1 unit load (note 4) d i cc v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a note: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads mr 1.5 data 0.4 cp 1.5 note: unit load is d i cc limit speci?ed in dc electrical speci?cations table, e.g., 360 m a max at 25 o c. prerequisite for switching speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types maximum clock frequency (figure 1) f max - 2 6 - - 5 - 4 - mhz 4.5 30 - - 25 - 20 - mhz 6 35 - - 29 - 23 - mhz mr pulse width (figure 1) t w - 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns CD74HC273, cd74hct273
5 clock pulse width (figure 1) t w - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns set-up time data to clock (figure 5) t su - 2 60 - - 75 - 70 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns hold time, data to clock (figure 5) t h -23--3-3-ns 4.5 3 - - 3 - 3 - ns 63--3-3-ns removal time, mr to clock t rem - 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns hct types maximum clock frequency (figure 2) f max - 4.5 25 - - 20 - 16 - mhz mr pulse width (figure 2) t w - 4.5 12 - - 15 - 18 - ns clock pulse width (figure 2) t w - 4.5 20 - - 25 - 30 - ns set-up time data to clock (figure 6) t su - 4.5 12 - - 15 - 18 - ns hold time, data to clock (figure 6) t h - 4.5 3 - - 3 - 3 - ns removal time, mr to clock t rem - 4.5 10 - - 13 - 15 - ns switching speci?cations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max hc types propagation delay, clock to output (figure 3) t plh , t phl c l = 50pf 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 30 38 ns c l = 15pf 5 12 - - - ns propagation delay, mr to output (figure 3) t phl c l = 50pf 2 - 150 190 225 ns 4.5 - 30 38 45 ns 6 - 26 30 38 ns output transition time (figure 3) t tlh , t thl c l = 50pf 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns input capacitance c i ---1010 10pf maximum clock frequency f max c l = 15pf 5 60 - - - mhz prerequisite for switching speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max CD74HC273, cd74hct273
6 power dissipation capacitance (notes 5, 6) c pd - 5 25 - - - pf hct types propagation delay, clock to output (figure 4) t plh , t phl c l = 50pf 4.5 - 30 38 45 ns c l = 15pf 5 12 - - - ns propagation delay, mr to output (figure 4) t phl c l = 50pf 4.5 - 32 40 48 ns output transition time t tlh , t thl c l = 50pf 4.5 - 15 19 22 ns input capacitance c in ---1010 10pf maximum clock frequency f max c l = 15pf 5 50 - - - mhz power dissipation capacitance (notes 5, 6) c pd - 5 25 - - - pf notes: 5. c pd is used to determine the dynamic power consumption, per flip-flop. 6. p d =c pd v cc 2 f i + ? (c l v cc 2 +f o ) where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?cations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width figure 3. hc and hcu transition times and propaga- tion delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% CD74HC273, cd74hct273
7 figure 5. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 6. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits test circuits and waveforms (continued) t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v CD74HC273, cd74hct273
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated
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